Showing posts with label Why CISC. Show all posts
Showing posts with label Why CISC. Show all posts

Sunday, 22 January 2012

Pipelining


  • Fetch instruction

  • Decode instruction

  • Calculate operands (i.e. EAs)

  • Fetch operands

  • Execute instructions

  • Write result

  • Overlap these operations


Two Stage Instruction Pipeline


Pentium 4 Cache



  • Pentium (all versions) – two on chip L1 caches


—   Data & instructions