- A communication pathway connecting two or more devices
- Often grouped
---- A number of channels in one bus
---- e.g. 32 bit data bus is 32 separate single bit channels
Data Bus :
- Carries data
---- Remember that there is no difference between “data” and “instruction” at this level.
- Width is a key determinant of performance
---- 8, 16, 32, 64 bit
Address bus :
- Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory
- Bus width determines maximum memory capacity of system
e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus :
- Control and timing information
---- Memory read/write signal
---- Interrupt request
---- Clock signals
Bus Interconnection Scheme
Single Bus Problems
- Lots of devices on one bus leads to:
— Propagation delays
— Long data paths mean that co-ordination of bus use can adversely affect performance
— If aggregate data transfer approaches bus capacity
- Most systems use multiple buses to overcome these problems
Traditional Bus Architecture
High Performance Bus
Bus Types
- Dedicated
--- Separate data & address lines
- Multiplexed
--- Shared lines
--- Address valid or data valid control line
Advantage
--- Fewer lines
Disadvantages
--- More complex control
--- Ultimate performance
Bus Arbitration
- More than one module controlling the bus
- e.g. CPU and DMA controller
- Only one module may control bus at one time
- Arbitration may be centralised or distributed
Centralised Arbitration
- Single hardware device controlling bus access
--- Bus Controller
--- Arbiter
- May be part of CPU or separate
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