Interrupts

Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing

• Program

e.g. overflow, division by zero

• Timer :Generated by internal processor timer

Used in pre-emptive multi-tasking I/O from I/O controller

• Hardware failure

e.g. memory parity error

Interrupt Cycle :

• Added to instruction cycle


• Processor checks for interrupt

          ---Indicated by an interrupt signal

• If no interrupt, fetch next instruction


• If interrupt pending:

         ---Suspend execution of current program

Computer Components:

Top Level View

Instruction Cycle :

The IAS computer operated by a repetitively performing an instruction cycle .Each instruction cycle consists of two sub cycles.

1. Fetch Cycle


2. Execute Cycle

Basic Instruction cycle:

Fetch Cycle :

During the Fetch cycle, the opcode of the next instruction is loaded