Interrupts

Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing

• Program

e.g. overflow, division by zero

• Timer :Generated by internal processor timer

Used in pre-emptive multi-tasking I/O from I/O controller

• Hardware failure

e.g. memory parity error

Interrupt Cycle :

• Added to instruction cycle


• Processor checks for interrupt

          ---Indicated by an interrupt signal

• If no interrupt, fetch next instruction


• If interrupt pending:

         ---Suspend execution of current program

         ---Save context

         ---Set PC to start address of interrupt handler routine

         ---Process interrupt

         ---Restore context and continue interrupted program

Instruction Cycle with Interrupts

Instruction Cycle (with Interrupts) - State Diagram

Multiple Interrupts

Disable interrupts

---- Processor will ignore further interrupts whilst processing one interrupt

---- Interrupts remain pending and are checked after first interrupt has been processed

---- Interrupts handled in sequence as they occur

Define priorities

---- Low priority interrupts can be interrupted by higher priority interrupts

---- When higher priority interrupt has been processed, processor returns to previous interrupt

Connecting

• All the units must be connected


• Different type of connection for different type of unit

—   Memory

—   Input/Output

—   CPU