Instruction Cycle with Indirect

Indirect Cycle

• May require memory access to fetch operands


• Indirect addressing requires more memory accesses


• Can be thought of as additional instruction subcycle

Instruction Cycle with Indirect



Instruction Cycle State Diagram

Interrupts

Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing

• Program

e.g. overflow, division by zero

• Timer :Generated by internal processor timer

Used in pre-emptive multi-tasking I/O from I/O controller

• Hardware failure

e.g. memory parity error

Interrupt Cycle :

• Added to instruction cycle


• Processor checks for interrupt

          ---Indicated by an interrupt signal

• If no interrupt, fetch next instruction


• If interrupt pending:

         ---Suspend execution of current program