Instruction Cycle with Indirect

Indirect Cycle

• May require memory access to fetch operands


• Indirect addressing requires more memory accesses


• Can be thought of as additional instruction subcycle

Instruction Cycle with Indirect



Instruction Cycle State Diagram

Data Flow (Instruction Fetch)

• Depends on CPU design


• In general:


• Fetch

—   PC contains address of next instruction

—   Address moved to MAR

—   Address placed on address bus

—   Control unit requests memory read

—   Result placed on data bus, copied to MBR, then to IR

—   Meanwhile PC incremented by 1

Data Flow (Data Fetch)

• IR is examined


• If indirect addressing, indirect cycle is performed

—   Right most N bits of MBR transferred to MAR

—   Control unit requests memory read

—   Result (address of operand) moved to MBR

  Data Flow (Fetch Diagram)



Data Flow (Indirect Diagram)

Data Flow (Execute)

• May take many forms


• Depends on instruction being executed


• May include

—   Memory read/write

—   Input/Output

—   Register transfers

—   ALU operations

Data Flow (Interrupt)

• Simple


• Predictable


• Current PC saved to allow resumption after interrupt


• Contents of PC copied to MBR


• Special memory location (e.g. stack pointer) loaded to MAR


• MBR written to memory


• PC loaded with address of interrupt handling routine


• Next instruction (first of interrupt handler) can be fetched

Data Flow (Interrupt Diagram)