Pipelining

• Fetch instruction


• Decode instruction


• Calculate operands (i.e. EAs)


• Fetch operands


• Execute instructions


• Write result


• Overlap these operations

Two Stage Instruction Pipeline

Pentium 4 Cache

• Pentium (all versions) – two on chip L1 caches

—   Data & instructions

• Pentium 4 – L1 caches

—   8k bytes

—   64 byte lines

—   four way set associative

• L2 cache

—   Feeding both L1 caches

—   256k

—   128 byte lines

—   8 way set associative

Pentium 4 Diagram (Simplified)

Pentium 4 Core Processor

• Fetch/Decode Unit

—   Fetches instructions from L2 cache

—   Decode into micro-ops

—   Store micro-ops in L1 cache

• Out of order execution logic

—   Schedules micro-ops

—   Based on data dependence and resources

—   May speculatively execute

• Execution units

—   Execute micro-ops

—   Data from L1 cache

—   Results in registers

• Memory subsystem

—   L2 cache and systems bus

Why CISC ?

• Compiler simplification?

—   Disputed…

—   Complex machine instructions harder to exploit

—   Optimization more difficult

• Smaller programs?

—   Program takes up less memory but…

—   Memory is now cheap

—   May not occupy less bits, just look shorter in symbolic form

–     More instructions require longer op-codes

–     Register references require fewer bits

RISC Characteristics

• One instruction per cycle


• Register to register operations


• Few, simple addressing modes


• Few, simple instruction formats


• Hardwired design (no microcode)


• Fixed instruction format


• More compile time/effort